This invention relates, in general, to integrated circuits and, more particularly, to detection of electromigration in integrated circuits.
Electromigration has been identified as a primary failure mode of interconnect lines used in semiconductor integrated circuits. This high current-density induced mass-transport phenomenon manifests itself as voids, hillocks, or open circuits, due to a momentum exchange between conduction electrons and host metal atoms. As device dimensions shrink, the interconnect cross-sectional area reduces as well. This results in increased current densities. As the current densities reach the order 1 MA/cm2, metallic lines start to fail as a result of void and hillock formation. This phenomenon, electromigration, is the result of mass transport due to large current densities. For typical room-temperature operation, this failure can be avoided by using larger feature sizes, biasing in a low-power mode, and/or replacing the Al or Cu with Ag. Traditionally, electromigration has been studied with a set of parallel interconnects or with a belch structure. Under elevated current stress and temperature stress, the interconnects are made to fail, and the failure point is studied after the event. It would be beneficial to study and/or predict the evolution of an electromigration failure, but this would require knowing where void and hillock formation are beginning along a long interconnect. Typically, this is very difficult to determine since the initial stages of electromigration present only subtle changes in optical or scanning electron micrographs.
In accordance with one embodiment of the present invention, there is provided a method and apparatus for measuring resistance indicative of the presence or absence of the onset of electromigration in metal traces such as, for example, interlevel metallization in integrated circuits. In one aspect of this embodiment, the location of electromigration failure in the metal trace is determined by measuring the resistance of short segments of the metal trace simultaneously. Thus, the metal trace is divided into small segments and the resistances of each small segment are repeatedly measured.
By way of example, the metal trace is divided into 100 segments. In another example the metal trace is divided into 1,000 segments. The number of segments into which the metal trace is divided is not a limitation of the present invention. Thus, the metal segment can be divided into thousands of segments, tens of thousands of segments, or even more segments. Preferably, the segments are less than one micrometer in length. A polling architecture is used to maximize the number of segments that can be monitored in real time. A rise in resistance in a particular segment indicates the early stages of void and hillock formation. Since the particular location is known, optical and electron microscopy can be used periodically to examine the evolution of the interconnect morphology. It should be understood that the metallic composition of the metal trace is not a limitation. For example, the metal trace can be copper, aluminum, or the like. In addition, the particular substrate on which the interconnects or the circuitry used to monitor the resistance is manufactured is not a limitation of the present invention. For example, the substrate can be silicon, germanium, silicon germanium, silicon on insulator (SOI), gallium arsenide and other compound semiconductor substrates, or the like.
A device for studying and/or predicting electromigration in integrated circuits includes at least one conductive trace with a multiplicity of connections to conductors. With a known current through the trace, the voltage drop between each pair of adjacent conductors is indicative of the resistance. Repeatedly monitoring the resistance permits a resistance change to be detected as an indication of electromigration. Preferably, according to one embodiment of the invention, the voltage drops across adjacent conductors are output to an analog multiplexer. Resistance indicating circuitry is stepped from the voltage across one pair of conductors output to another by a polling clock signal applied to the multiplexer.
In one embodiment, the voltage drop detected at each segment of the trace is amplified and the amplified voltage is used to indicate resistance of each trace segment defined between the connections to the conductors.
Preferably, in accordance with one embodiment of the invention, two substantially parallel traces are formed on a substrate and each has a multiplicity of connections to conductors for the observance of the resistance as indicated by the voltage drop from one conductor to the next. In another embodiment, a resistance meter is coupled to each pair of adjacent conductors along the length of the trace or traces. The resistance meter may be a resistance indicator dependent on voltage from one conductor to the next as applied through a multiplexer as previously described.
In accordance with one embodiment of the present invention, the circuitry used for measuring the resistance of the metal traces is external to the semiconductor material on which the metal trace is formed. In accordance with another embodiment of the present invention, the circuitry used for measuring the resistance of the metal trace is monolithically integrated on the semiconductor material on which the metal trace is formed. This integrated approach allows the most detailed monitoring of the interconnect segments, however it also requires that the circuitry operate at elevated temperatures. In yet another embodiment of the present invention, a portion of the circuitry used for measuring the resistance of metal trace is monolithically integrated on the semiconductor material and a portion is external to the semiconductor material on which the metal trace is formed. In both of these embodiments, the circuitry for monitoring the resistance of each segment traces monitors the resistance in real time while under temperature and current stress.
An advantage of the present invention is that it allows characterization of electromigration in real time as a function of device topographiesxe2x80x94wafer level, circuit, and package parts. Further, the precise location of the initial stages of void and hillock formation can be determined. The approach of this invention allows for a model to be consistent and valid across all topographies proposed. The insight gained is immediately incorporated into process and reliability improvement efforts.
The above and further objects and advantages of the invention will be better understood in view of the following detailed description of at least one preferred embodiment taken in consideration with the accompanying drawings.